The present invention relates to a television synchronization generator, and more particularly, to one used in a portable color camera operating on PAL-B standards.
In PAL-B in order to minimize a visible dot crawl in the displayed picture, it is necessary to derive an offset subcarrier that differs from subcarrier frequency by a decrement of the frame frequency (25 Hz). This offset subcarrier is used as a reference to which scanning signal frequencies are locked in accordance with certain mathematical relationships.
A common method of deriving the offset subcarrier involves a pair of balanced modulator integrated circuits, driven by two subcarrier (SC) signals in quadrature phase with respect to each other and two frame frequency signals in quadrature phase with respect to each other. Subcarrier frequency signals are suppressed in the modulator outputs, leaving only sum and difference frequency signals. Outputs from the two modulators are combined in such a way that the sum frequency signals are cancelled and the difference frequency signals are added in phase. The resultant difference frequency of SC frequency minus frame frequency is the desired frequency for the offset subcarrier.
The waveforms driving the modulators are sinusoidal, requiring filters to derive them from the available rectangular waves. Phase shifting circuits are used to produce the required quadrature relationships. Finally, the sinusoidal offset subcarrier is squared by a limiter to make a suitable rectangular wave for driving a digital frequency divider. The number of parts and consequent space requirements, as well as power required, made it desirable to consider other approaches.
There are other approaches in the prior art, including a method that begins with a four times subcarrier frequency signal and involves periodic removal of cycles from this signal to form an offset frequency signal. This offset frequency is then divided down to line frequency. The pulse removal operation results in periodic phase step perturbations at the field rate that are 112 nanoseconds in magnitude. These perturbations must be smoothed out by a phase-lock loop including a clock oscillator, which produces the clock frequency signal for the sync pulse generator. The bandwidth of such a loop must be less than the field frequency (50 Hz), in order to achieve adequate smoothing. Such a narrow bandwidth precludes the loop from attenuating any 50 Hz crosstalk, such as from the power line or from the field frequency circuits, introduced into the clock oscillator or elsewhere into the phase-lock loop other than the reference input. It is desirable from this standpoint that any perturbations in the signal fed to a clock oscillator phase-lock loop be as small as possible and at as high a frequency as possible. These characteristics also mean that the lock up time can be minimized, since wider bandwidth makes faster lock up possible.
It is therefore desirable to provide a PAL synchronization generator which requires a minimum of components, has low power consumption, and has minimal phase perturbations in its outputs.